부산대학교 도서관

As the number of cores in a chip multiprocessor increase, the directory area overhead becomes excessive. Current research shows that directory area can be reduced by tracking private entries with coarse-grain region entries. The insight is that contiguous memory blocks are often accessed by a single core. In order to indicate which blocks the region owner has cached, a bit vector format is applied in the dual-grain directory (DGD). However, this limits scalability and is incompatible with the latest scalable directories. In this paper, we propose a scalable short-entry dual-grain coherence directory (SS-DGD). In private region entries, a counter is used instead of the original bit vector. To reduce the directory area, we use a separate short-entry directory to store private block entries with a pointer format and region entries with counters. The detailed simulation-based study in 64-core CMPs shows that our proposal can reduce the area overhead by 29.9% compared with DGD.