학술논문
Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs
Document Type
Conference
Author
Source
2018 48th European Solid-State Device Research Conference (ESSDERC) Solid-State Device Research Conference (ESSDERC), 2018 48th European. :242-245 Sep, 2018
Subject
Language
ISSN
2378-6558
Abstract
This work explores, for the first time, wafer level variability of the gate leakage current in advanced FD-SOI MOSFETs. A simple model based on WKB approximation is introduced to model the leakage current and its variance. IL/HK variability segregation is presented using split C-V and gate current data without any dedicated test structures.