학술논문

Integration challenges of Cu pillars with extreme wafer thinning for 3D stacking and packaging
Document Type
Conference
Source
2011 IEEE 13th Electronics Packaging Technology Conference Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th. :25-28 Dec, 2011
Subject
Components, Circuits, Devices and Systems
Copper
Silicon
Three dimensional displays
Surfaces
Bonding
Coatings
Resists
Language
Abstract
In this paper, we report on the development of Cu pillars and their impact on the subsequent thinning process for 3D applications. As the Cu pillars have a height of tens of microns (typically between 50–100µm), controlling the total thickness variation (TTV) after wafer thinning is becoming even more challenging. The Cu pillars are processed after completion of the Back End of Line (BEOL) with a target thickness of 50µm for a diameter of 80µm and a pitch of 200µm. The key challenge for 3D integration is the control of the wafer TTV after back grinding in order to allow TSV reveal. After optimization of the temporary wafer bonding in presence of high topography induced by 50µm high Cu pillars, a TTV after thinning below 5µm is achieved, which is comparable to the TTV obtained after wafer thinning without topography.