학술논문
Stress Memorization Technique (SMT) Optimization for 45nm CMOS
Document Type
Conference
Author
Source
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on. :78-79 2006
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
In this paper, we present an optimization path of stress memorization technique (SMT) for 45nm node and below using a nitride capping layer. We demonstrate that the understanding of coupling between nitride properties, dopant activation and poly-silicon gate mechanical stress allows enhancing nMOS performance by 7% without pMOS degradation. In contrast to previously reported works on SMT (Chen et al., 2004) - (Singh et al., 2005), a low-cost process compatible with consumer electronics requirements has been successfully developed