학술논문

Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND
Document Type
Conference
Source
2023 IEEE International Memory Workshop (IMW) Memory Workshop (IMW), 2023 IEEE International. :1-4 May, 2023
Subject
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Silicon compounds
Three-dimensional displays
Ferroelectric materials
Logic gates
Programming
Boosting
Capacitance
Language
ISSN
2573-7503
Abstract
In this paper, we optimize the retention in gate stacks including ferroelectric materials for program / erase boosting. The improved program performance by exploiting ferroelectricity in a material used for charge storage medium has been confirmed. However, the retention properties of such materials still need to be improved. As an alternative, we propose a dual charge trapping layer made of thin Si 3 N 4 / ferroelectric high-K material that can keep the retention to the level of a conventional ONO gate stack, while benefiting from the boosting effect. For application as blocking oxide, the improvement in program / erase due to capacitance boosting could also be observed, but the use of a thick high-K material at this position causes retention issues that are difficult to solve. Alternatively, placing a thin high-K below a SiO 2 blocking layer can improve programming without penalty in retention. This calls for developing ultra-thin high-K materials with ferroelectric properties for further improvement.