학술논문

Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults
Document Type
Periodical
Author
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 42(8):2752-2760 Aug, 2023
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Circuit faults
Logic gates
Test pattern generators
Iterative methods
Compaction
Benchmark testing
Test data compression
Single-cycle gate-exhaustive faults
test compaction
test data compression
test generation
Language
ISSN
0278-0070
1937-4151
Abstract
Cell-aware and gate-exhaustive faults are used for modeling defects whose activation requirements are more complex than those of stuck-at or transition faults. The number of cell-aware or gate-exhaustive faults targeted for test generation has to be bounded to avoid the generation of excessive numbers of tests. In this context, it is advantageous to be able to estimate the number of tests in advance based on the number of target faults, and avoid targeting an excessive number of faults that will result in an excessive number of tests. This article suggests such an estimate for the scenario where test generation is applied iteratively using subsets of single-cycle gate-exhaustive faults such that the detection of every additional subset will provide a meaningful increase in the coverage of the test set. Based on the results of iteration $I-1$ , the estimate predicts the number of tests that will be obtained in iteration $I$ . Test generation can terminate, without generating additional tests, when the estimate indicates that the number of tests will exceed a preselected bound. Experimental results for benchmark circuits demonstrate the accuracy of the estimate.