학술논문

Test Insertion for Dynamic Test Compaction
Document Type
Periodical
Author
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 43(4):1302-1306 Apr, 2024
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Circuit faults
Compaction
Logic gates
Test pattern generators
Benchmark testing
Tail
Fault detection
Dynamic test compaction
single-cycle gate-exhaustive faults
static test compaction
test generation
Language
ISSN
0278-0070
1937-4151
Abstract
Dynamic test compaction techniques are used during test generation to ensure that each test detects as many faults as possible, resulting in the smallest possible number of tests. As additional tests are generated, detected faults are removed from consideration, and it is expected that the number of detected faults per test would decrease. A nonmonotonic decrease in this parameter indicates that the test set may be larger than necessary since tests detect fewer faults than possible. To ensure a monotonic decrease, this article suggests a dynamic test compaction technique that inserts every new test into the test set at a position based on the number of faults it detects. After inserting a test, the procedure adjusts the test and all the tests that follow it to detect more faults. Experimental results to demonstrate the effectiveness of test insertion as a dynamic test compaction technique are presented for single-cycle gate-exhaustive faults in benchmark circuits. The large number of faults brings out the ability of test insertion to contribute to test compaction.