학술논문

Testability Evaluation for Local Design Modifications
Document Type
Periodical
Author
Source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 32(1):195-199 Jan, 2024
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Circuit faults
Test pattern generators
Fault diagnosis
Iterative methods
Compaction
Design for testability
Benchmark testing
Logic design
Iterative synthesis
test compaction
test generation
undetectable faults
Language
ISSN
1063-8210
1557-9999
Abstract
Iterative synthesis consists of local design modifications to improve design parameters or correct design errors. Incremental test generation was suggested for evaluating the effects of the modifications on the testability of the design. This brief suggests that a fast (incomplete) procedure for identifying undetectable faults is effective in identifying that the testability will deteriorate because of a local design modification without performing test generation. Two experiments are carried out using a procedure that performs successive local design modifications. A modification is accepted only if it does not result in new undetectable faults, and other modifications are eliminated. The results for single stuck-at faults in benchmark circuits demonstrate that fast identification of undetectable faults is typically sufficient for preventing the fault coverage from decreasing because of the modifications.