학술논문
A New Twin Flash™ Cell for 2 and 4 Bit Operation at 63nm Feature Size
Document Type
Conference
Author
Nagel, N.; Muller, T.; Isler, M.; Pissors, V.; Sachse, J.-U.; Manger, D.; Caspary, D.; Parascandola, S.; Olligs, D.; Boubekeur, H.; Heinrichsdorff, F.; Bach, L.; Polei, V.; Gupta, J.; Pritchard, D.; Riedel, S.; Strassburg, M.; Deppe, J.; Bewersdorff-Sarlette, U.; Verhoeven, M.; Lattard, L.; Markert, M.; Ruttkowski, E.; Mikalo, R.; Willer, J.; Schulze, N.; Ludwig, C.; V. Kamienski, E.G.S.; Mikolajick, T.; Kusters, K.-H.; Shappir, A.; Shur, Y.; Lusky, E.; Eitan, B.
Source
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on. :1-2 Apr, 2007
Subject
Language
ISSN
1524-766X
Abstract
A 63nm Twin Flash memory cell with a size of 0.0225μm 2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ~100nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.