학술논문

Single Event Induced Multiple Bit Errors and the Effects of Logic Masking
Document Type
Periodical
Source
IEEE Transactions on Nuclear Science IEEE Trans. Nucl. Sci. Nuclear Science, IEEE Transactions on. 60(6):4192-4199 Dec, 2013
Subject
Nuclear Engineering
Bioengineering
Field programmable gate arrays
Single event transients
Single event upsets
Error analysis
Field programmable gate array (FPGA)
single event transient (SET)
single event upset (SEU)
synchronous design
Language
ISSN
0018-9499
1558-1578
Abstract
We apply a model and heavy-ion cross section data to predict the potential that one single event upset (SEU) will induce multiple bit errors (MBEs) by the next clock-cycle of a synchronous design.