부산대학교 도서관

Nowadays, process-induced stress is the preferential industrial method to enhance circuit performances. One of the most popular techniques is the strain induced by contact etch-stop layer. This technology induces a drain–current enhancement which depends on the device dimensions. This strong behavior has already been reported in the literature. In this paper, we propose a simple semianalytical physical model to understand the origin of this dependence and to highlight the physical limitations of the stress techniques. With this model, after a calibration, it would be possible to predict the MOSFET performance for a given transistor gate length. This approach is validated by experimental data and explains the reduction of the drain–current enhancement that is observed for ultrasmall gate-length MOSFET.