부산대학교 도서관

Server System-on-Chip (SoC) design technology is rapidly growing, catering to modern competitive market needs and delivering to broad portfolio from edge to cloud. Latest SoC processors are very powerful in compute and provide multiple new features. Built-in AI, advanced security, advanced I/O & ethernet, high throughput compute dense performance sensitive core, make end-to-end post-silicon validation of these SoCs complex. Functional post-silicon validation is an important pillar in ensuring the functionality of these breakthrough features and uncovering defects before shipping to customers. Along with ensuring architectural correctness, one of the goals of post-silicon validation is to stress test as many scenarios as possible, to ensure product quality within aggressive time-to-market (TTM). Postsilicon Functional Validation generally employs combinations of powerful OS based tools and test sequences to verify & validate complex SoC functions. Sometimes Functional Validation may use Synthetic validation frameworks, directly run on the SystemUnder-Test (SUT) to test architectural features, and verify the results. One such powerful framework in the Intel FV community is the Validation workload (ValWL), which provides set of validation applications, libraries, and configuration files to build pseudo-random tests covering a variety of system logic scenarios. ValWL is tightly coupled with System Validation Operating System, uses the kernel drivers and libraries, and runs completely on the SUT. With aggressive time-to-market trends and, it is imperative to optimize post-silicon validation execution for maximum coverage and efficiency. Discussed in this paper is the method to use the latest Hardware Accelerator IPs in the Xeon SoCs to optimize the ValWL Framework while validating the SUT. Validation efficiency is increased significantly increasing the confidence in the design while minimally impacting TTM.