학술논문
Building high performance transistors on carbon nanotube channel
Document Type
Conference
Author
Pitner, Gregory; Safron, Nathaniel; Chao, Tzu-Ang; Li, Shengman; Su, Sheng-Kai; Zeevi, Gilad; Lin, Qing; Chiu, Hsin-Yuan; Passlack, Matthias; Zhang, Zichen; Sathaiya, D. Mahaveer; Wei, Aslan; Gilardi, Carlo; Chen, Edward; Liew, San-Lin; Hou, Vincent D.-H.; Wu, Chung-Wei; Wu, Jeff; Lin, Zhiwei; Fagan, Jeffrey; Zheng, Ming; Wang, Han; Mitra, Subhasish; Philip Wong, H.-S.; Radu, Iuliana
Source
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023
Subject
Language
ISSN
2158-9682
Abstract
High-performance and scaled transistors on carbon nanotube (CNT) channel are enabled by the quality of device component modules. This paper advances each module by single-CNT control experiments reporting: (1) remarkable n-type contact resistance of 5.1 k$\Omega$/CNT(20.4$\Omega-\mu$m for 250 CNT/$\mu$m) at 20 nm contact length, (2) tunable N-and Pdoping of CNT with dielectric doping, (3) improvement in top-gate dielectric interface to CNT by channel cleaning, (4) demonstration of channel comprised of dense CNT array with reduced bundle density, and (5) analysis of CNT bandgap tradeoffs with variability control strategy. The first component-complete pMOS FET is demonstrated on high-density CNTs with up to 680 $\mu$A/$\mu$m at -0.7V VDS.