부산대학교 도서관

Forward error correction coding schemes have been used extensively in order to provide continuous and reliable telemetry data transfer from satellites to ground stations and guarantee reliable communications even at low signal-to-noise ratio regimes, where burst errors are dominant. Nevertheless, conventional bit-level channel coding can fail to provide downlink reliability against long error bursts in future high data rate radio frequency and optical (laser) links, especially when automatic repeat queuing strategies are either problematic or impossible due to specific service delay constraints. Packet-level erasure coding has been considered by the Consultative Committee for Space Data Systems (CCSDS) in CCSDS 131.5-O-1 experimental specification for application in high data rate near-earth and deep-space communications, since it can protect against long error bursts as they may come along with the effect of scintillation outages or transmission errors. Implementations of packet-level encoding and decoding so far exist only in software, running on a general-purpose CPU. In this article, we introduce and compare analytical descriptions of packet-level encoding algorithms suitable for hardware implementations. Based on these algorithmic descriptions, we introduce, for the first time, architectures for hardware acceleration of these functions that allow integration on a high-speed on-board data-processing chain with very low footprint. We validate our hardware implementations and demonstrate the efficiency of the proposed architectures on a Xilinx KCU105 development board, which is built around the commercial equivalent of a space-grade field-programmable gate array device. Apart from offloading packet-level encoding from the on-board embedded processor, the proposed accelerators achieve a significant speedup (over 80 times), when compared with on-board software implementations, by porting on some of the most commonly used and state-of-the-art space-qualified embedded processors.