학술논문
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration
Document Type
Conference
Author
Cho, Sung-Yong; Choi, Moon-Chul; Baek, Jaehyeok; An, Donggun; Kim, Sanghoon; Lee, Daewoong; Yang, Seongyeal; Kang, Gil-Young; Park, Juseop; Lee, Kyungho; Jung, Hwan-Chul; Cho, Gunhee; Lee, Chanyong; Kim, Hye-Ran; Shin, Yong-Jae; Park, Hanna; Lee, Sangyong; Kim, Jonghyuk; Won, Bokyeon; Mok, Jungil; Kim, Kijin; Lim, Unhak; Jin, Hong-Jun; Lee, YoungSeok; Kim, Young-Tae; Ha, Heonjoo; Ahn, Jinchan; Sung, Wonju; Jang, Yoontaek; Song, Hoyoung; Ban, Hyodong; Park, TaeHoon; Oh, Tae-Young; Yoo, Changsik; Hwang, SangJoon
Source
2024 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2024 IEEE International. 67:242-244 Feb, 2024
Subject
Language
ISSN
2376-8606
Abstract
GDDR memory has consistently maintained a leading position in delivering high performance: necessary for applications such as artificial intelligence, deep learning, and data centers. However, achieving an elevated I/O bandwidth, beyond the latest 27Gb/s GDDR6 [1], presents significant challenges in ensuring a sufficient I/O link budget. One solution is using multi-level pulse amplitude modulation (PAM) signaling. In the GDDR7 I/O specification, single-ended PAM3 signaling is used to achieve higher data rates as it can transfer data more than 58% faster, compared to non-return-to-zero (NRZ) signaling. Furthermore, PAM3 offers a 50% larger voltage sensing margin than PAM4, which was adopted for GDDR6X [2]. Therefore, PAM3 exhibits a higher potential for bandwidth extension, given that single-ended signaling is vulnerable to random noise and crosstalk.