학술논문
25.1 A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation
Document Type
Conference
Author
Kim, Kyunghoon; Chae, Joo-Hyung; Yang, Jaehyeok; Kang, Jihyo; Lee, Gangsik; Byeon, Sangyeon; Kim, Youngtaek; Kim, Boram; Kim, Dong-Hyun; Cho, Yeongmuk; Choi, Kangmoo; Park, Hyeongyeol; Ji, Junghwan; Jeong, Sera; Joo, Yongsuk; Cha, Jaehoon; Park, Minsoo; Kim, Hongdeuk; Park, Sijun; Kong, Kyubong; Kim, Sunho; Lee, Sangkwon; Chun, Junhyun; Kim, Hyungsoo; Cha, Seonyong
Source
2021 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2021 IEEE International. 64:344-346 Feb, 2021
Subject
Language
ISSN
2376-8606
Abstract
The demand for high-performance graphics systems used for artificial intelligence continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. Enabling GDDR6 DRAM to achieve data rates beyond 18Gb/s/pin [1] requires identifying and solving factors that affect the speed of a memory interface. Prior studies have showed that the memory interface is vulnerable from the signal integrity (SI) and power integrity (PI) perspective, since it is based on a parallel interface using single-ended signaling. Furthermore, circuit schemes to mitigate process, voltage, and temperature (PVT) variations in sub-nanometer DRAM process are required to improve performance. To achieve 24Gb/s/pin on a 1.35V DRAM process, this work proposes a GDDR6 DRAM with a half-rate clocking architecture and optimized I/O.