학술논문

Latch-Controlled Current Cell for Low Power Current-Steering D/A Converter
Document Type
Conference
Source
2012 UKSim 14th International Conference on Computer Modelling and Simulation Computer Modelling and Simulation (UKSim), 2012 UKSim 14th International Conference on. :655-659 Mar, 2012
Subject
Computing and Processing
Microprocessors
Switches
Arrays
Power demand
Decoding
Latches
Current cell
DAC
latch
power consumption
Language
Abstract
This paper introduces the design and implementation of a novel current cell in current-steering digital-to-analog converter (DAC). The current cell consists of current switch and source which are independently controlled by latch. A sequential switch-on process similar to thermometer decoding is implemented in source to reduce the power consumption. A 12-b DAC has been fabricated using a single-poly four-metal 0.35 µm CMOS process. Comparison with conventional DAC shows that the proposed DAC produces a power reduction in the order of 35% without degradation of linearity. Two sub-DACs are composed of 8-bit unary matrix type and 4-bit binary type. The least significant bits (LSB's) steer a binary array, while the most significant bits (MSB's) are thermometer coded and steer a unary array. The two major blocks of DAC circuit are the digital and the cell array block. With an increase in the number of bit, the most power in current steering DAC is consumed in the cell array block. Therefore, low power cell operation is essential to reduce the overall DAC power consumption.