부산대학교 도서관

Heterogeneous integration is the key technology which is applied in HPC, AI and Could computing applications. Through the die to die interconnection, such as ASIC to HBM and ASIC to ASIC. the higher I/O density, wider data transimission bandwidth between memory to active die and lower RC delay are reuqired in chiplet integration. However, the heterogeneous integration between different funtional dies which lead varius process challenges, such as multilayered Redistribution Layers (RDL) warpage control, surface coplanarization treatment, and solder joint capability during the die bond (DB) process. Hence, in this paper, we demonstrate the large size FO-MCM (MultiChip Module) package with 6 layers RDL which sucessfully overcome the non-wetting issue and warpage effect by optimized RDL technology and compatible glass carrier selection during wafer process. In this study, we demonstrate Fan-out MCM (MultiChip-Module) with 6 layers RDL by 2/2 um line/space, meanwhile, the warapge effect has decreased 39% by particular glass which has the compatible CTE parameter and the thickness. Besides, in this experiment, we assess chip module warpage performance during reflow high temperature 250C of chip last FO-MCM, that is important for C4 bump non-wetting phenomenon when chip module bonding to substrate or directly SMT bonding to PCB. This multilayered RDL with the compatible glass technology bring a potential benefit to improve the TTV and warpage effect on RDL surface. The results of the reliability test including TCT 1000 cycle, u-HAST 192 hours and HTSL 1000 hours are qualified in this experiment. Undoubtedly, Heterogeneous integration with multi-layer Fan-Out RDL is the mainstream for the AI, Could computing and high bandwidth memory integration in the IC package industry, by utilizing this innovative Multi-layer RDL with the compatible glass technology, the stability and yield of the fine pitch die bond will be improved obviously.