학술논문

A Self-Adaptive Dual-ILRO Clock-Recovery Technique for Two-Tone Battery-Free Crystal-Free Neural-Recording SoC
Document Type
Periodical
Source
IEEE Transactions on Biomedical Circuits and Systems IEEE Trans. Biomed. Circuits Syst. Biomedical Circuits and Systems, IEEE Transactions on. 18(1):39-50 Feb, 2024
Subject
Bioengineering
Components, Circuits, Devices and Systems
Clocks
Wireless communication
Injection-locked oscillators
Wireless power transfer
System-on-chip
Battery-free
clock recovery
crystal-free
injection locking
self-adaptive
wireless neural recording
wireless power transfer (WPT)
Language
ISSN
1932-4545
1940-9990
Abstract
Wireless implantable devices are widely used in medical treatment, which should meet clinical constraints such as longevity, miniaturization, and reliable communication. Wireless power transfer (WPT) can eliminate the battery to reduce system size and prolong device life, while it's challenging to generate a reliable clock without a crystal. In this work, we propose a self-adaptive dual-injection-locked-ring-oscillator (dual-ILRO) clock-recovery technique based on two-tone WPT and integrate it into a battery-free neural-recording SoC. The 2$\text{nd}$-order inter-modulation (IM2) component of the two WPT tones is extracted as a low-frequency reference for battery-free SoC, and the proposed self-adaptive dual-ILRO technique extends the lock range to ensure an anti-interference PVT-robust clock generation. The neural-recording SoC includes a low-noise signal acquisition unit, a power management unit, and a backscatter circuit to perform neural signal recording, wireless power harvesting, and neural data transmission. Benefiting from the 6.4 $\mu$W low power of the clock recovery circuit, the overall SoC power is cut down to 49.8 $\mu$W. In addition, the proposed clock-recovery technique enables both signal acquisition and uplink communication to perform as well as that synchronized by an ideal clock, i.e., an effective number of 9.6 bits and a bit error rate (BER) less than 4.8 $\times\, 10^{-7}$ in chip measurement. The SoC takes a die area of 2.05 mm$^{2}$, and an animal test is conducted in a Sprague-Dawley rat to validate the wireless neural-recording performance, compared to a crystal-synchronized commercial chip.