학술논문
Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology
Document Type
Conference
Author
Source
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Solid-state device research conference Solid-State Device Research Conference, 2004. ESSDERC 2004. Proceeding of the 34th European. :137-140 2004
Subject
Language
Abstract
In this paper, we present a study of the effects of strained contact etch stop layer on 65 nm CMOS transistor performance. It is found that the nitride layer above the transistor can improve the transistor drive current by 8.5% for NMOS and 6% for PMOS. By combining a complete electrical analysis, mechanical modeling and quantum simulations, we have obtained a detailed understanding of how transistor layout rules influence the strain enhancements.