부산대학교 도서관

Ring oscillator circuits are useful for the characterization of MOS transistors under switching operation. Accurate characterization of per-gate variation becomes difficult when the ring oscillator consists of many stages or contains heterogeneity. We propose a homogeneous ring oscillator structure with a staggered layout for the accurate characterization of per-gate characteristics. Using a header transistor instead of a NAND gate for oscillation control, our proposed structure can realize a 3-stage RO where the three stages have equal delay contributions. Measurement results from a 65 nm test chip confirm our proposed structure for gate-level characterization.