학술논문
Noise-robust hardware implementation of neural networks
Document Type
Conference
Source
2015 International Joint Conference on Neural Networks (IJCNN) Neural Networks (IJCNN), 2015 International Joint Conference on. :1-8 Jul, 2015
Subject
Language
ISSN
2161-4393
2161-4407
2161-4407
Abstract
Efficient hardware implementations of neural networks are of high interest. Stochastic computing is an alternative to conventional digital logic that allows to exploit the intrinsic parallelism of neural networks using few hardware resources. We present a new stochastic methodology that extends the capabilities of classical stochastic computing. In particular, the present approach exhibits practically total immunity to noise. This is demonstrated evaluating the influence of the noise on the system's performance for a mathematical regression task.