학술논문

Effects of the NoC architecture in the performance of NoC-based MPSoCs
Document Type
Conference
Source
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on. :431-434 Dec, 2014
Subject
Components, Circuits, Devices and Systems
Routing
Topology
Jitter
Transform coding
Ports (Computers)
Random access memory
Clocks
NoC-based MPSoC
NoCs
routing
topology
performance evaluation
Language
Abstract
The goal of this work is to evaluate the impact of multiple Network-on-Chip (NoC) architectural parameters over the performance of applications running on Multiprocessors Systems-on-Chip (MPSoCs) using message passing as communication protocol. Nowadays, MPSoCs have so many constraints of performance that bus-based communications are not able to achieve the full potential of MPSoCs, therefore, the adoption of NoCs is a trend for the communication infrastructure in MPSoCs due to their performance compared to bus-based architectures and scalability compared to crossbar-based architectures. However, there is an important gap in the literature with works evaluating the impact of NoC parameters in the performance of applications running in MPSoCs. This work proposes the evaluation of how different NoC parameters affect applications running in a real MPSoC, trying to answer the following question: how does a given NoC parameter affect the performance of the MPSoC?