학술논문
Approaches to extra low voltage DRAM operation by SOI-DRAM
Document Type
Periodical
Author
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 45(5):1000-1009 May, 1998
Subject
Language
ISSN
0018-9383
1557-9646
1557-9646
Abstract
The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-/spl mu/m 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.