부산대학교 도서관

This letter describes a fully synthesizable fractional- $N$ multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer- $N$ and fractional- $N$ operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.