부산대학교 도서관

This article introduces a high-accuracy phase and amplitude detection circuit for 5G phased-array calibration. By utilizing a 39 GHz–150 kHz down-conversion scheme, the phase and amplitude information are detected separately with a phase-to-digital converter (PDC) and an analog-to-digital converter (ADC). In addition, to reduce the number of reference signals, a divide-by-4 injection-locked frequency divider (ILFD) using a transformer-based injection-enhancing technique is implemented for wideband reference signal generation. This ILFD realizes a wide locking range of 16.3–23.4 GHz (35.8%) with 5.05-mW power consumption. The detection circuit achieves less than 0.049° and 0.036-dB detection rms errors at 39 GHz. The wideband high-accuracy detection is also achieved from 37 to 43.5 GHz. The total power consumption is 50 mW with a 1-V VDD. The total core area is 1.43 $\text {mm}^{2}$ in a 65-nm CMOS process.