부산대학교 도서관

This paper presents a pipeline analog to digital converter (ADC) consisting of five stages with 2.5 effective bit resolution. Several techniques were combined for the reduction of the power consumption and to preserve the converter linearity. To reduce the power consumption, the circuit has two scaled operational transconductance amplifiers (OTAs), which are shared by the first four pipeline stages. The last fifth stage is a single decoder with 2.5 effective bits. Each OTA includes additional circuitry to adapt the power consumption according to the stage that uses the OTA. This technique changes the bias current depending on the stage in operation. The ADC was optimized to obtain 11-bit resolution with frequencies from 1 kHz to 10 MHz. The technology used to simulate the ADC is a 3.3 V 0.35 μm CMOS process and the circuit consumes 17.9 mW at 20 MSample/s sampling rate. With this resolution and sampling rate, it achieves 67.28 dB SNDR and 10.88 bit ENOB at 0.1 MHz input frequency. The Figure of Merit is 0.473 pJ/step.