학술논문
Performance analysis of high-speed MOS transistors with different layout styles
Document Type
Conference
Author
Source
2005 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and systems Circuits and Systems (ISCAS), 2005 IEEE International Symposium on. :3688-3691 Vol. 4 2005
Subject
Language
ISSN
0271-4302
2158-1525
2158-1525
Abstract
Several layout schemes for MOS transistors have been investigated and compared in terms of speed and layout area. Among them, the so-called closed, donut or doughnut transistors have been characterized, obtaining an analytical expression for the calculation of the equivalent W/L ratio for a general n-side regular polygonal-shape. The comparisons show that with quasi-minimum dimension transistors and L=0.35 /spl mu/m, reductions of up to 81% on the drain area can be achieved with an increase of only a 10% on the total layout area for given W and L. An application improving the switching speed of an output multiplexer is shown.