학술논문
Minimizing interposer warpage by process control and design optimization
Document Type
Conference
Author
Source
2014 IEEE 64th Electronic Components and Technology Conference (ECTC) Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th. :33-40 May, 2014
Subject
Language
ISSN
0569-5503
2377-5726
2377-5726
Abstract
An analytical model simulating the bowing at wafer or thin die level was applied to imec's 3D interposer technology. The calibration methodology is explained. A good correlation between simulation and measurement has been found at different stages during the processing. Secondly, a model combining all the interposer features was used to simulate the bowing induced at wafer and thin die level. Finally, the model is used to provide some recommendations to mitigate the interposer bowing without any drastic change in the structure or impact onto its performances.