부산대학교 도서관

Multi-level cell (MLC) is an attractive method to increase the memory storage density and reduce the cost per bit. Write disturb rate (WDR) and large writing step counts are the main challenge to implement MLCs. In this article, a three-bit spin-orbit torque magnetic random-access memory (SOT-MRAM)-based MLC structure termed as triple level cell (TLC) is proposed. The majority of the bits in TLC require two steps of writing for storage, and the cell exhibits WDR less than $10^{-8}$ . The performance evaluation of the proposed structure is done on the SPICE framework utilizing a Verilog-A model for the structure. The proposed TLC device is 96% and 92% more energy efficient than spin transfer torque (STT)-based TLC and STT-/SOT-based TLC structures, respectively. The worst case write latency of the proposed TLC is 2 ns that shows 88% improvement compared to the recently published STT-/SOT-based TLC-MRAM. The variability analysis performed using Monte Carlo simulations shows sufficient margins between various writing currents employed for switching the stacked magnetic tunnel junctions (MTJs) that signify the reliable switching of the different bits in the TLC.