부산대학교 도서관

A front-end electronics module (FEM) has been developed for the PHENIX Pad Chamber. The module's control functions are performed by the heap manager unit, an FPGA-based circuit on the FEM. Each FEM processes signals from 2160 channels of front-end electronics (FEE). Data readout and formatting are performed by an additional FPGA-based circuit on the FEM. Three external systems provide initialization, timing, and data information via serial interfaces. This paper discusses the application of the heap manager, data formatter, and serial interfaces to meet the specific control and data readout needs of the Pad Chamber subsystem. Unit functions, interfaces, timing, data format, and communication rates are discussed. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling and FPGA implementation and programming are presented.