학술논문
Specificities of linear Si QD arrays integration and characterization
Document Type
Conference
Author
Niebojewski, H.; Bertrand, B.; Nowak, E.; Bedecarrats, T.; Paz, B. Cardoso; Contamin, L.; Mortemousque, P.A.; Labracherie, V.; Brevard, L.; Sahin, H.; Charbonnier, J.; Thomas, C.; Assous, M.; Casse, M.; Urdampilleta, M.; Niquet, Y.-M.; Perruchot, F.; Gaillard, F.; De Franceschi, S.; Meunier, T.; Vinet, M.
Source
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :415-416 Jun, 2022
Subject
Language
ISSN
2158-9682
Abstract
The low temperature operation of quantum computing devices implies developing characterization protocols, from extensive statistical tests to targeted device screening at cryogenic temperature. This paper reviews major integration constraints arising in linear Si quantum dots arrays and their implication on both the device operation and electrical characterization.