학술논문
A 2.7 mW/Channel 48–1000 MHz Direct Sampling Full-Band Cable Receiver
Document Type
Periodical
Author
Wu, J.; Cusmai, G.; Chou, A.W.; Wang, T.; Shen, B.; Periasamy, V.; Hsieh, M.; Chen, C.; He, L.; Tan, L.K.; Padyana, A.; Yang, V.C.; Unruh, G.; Wong, J.K.L.; Hung, B.J.; Brandolini, M.; Lin, M.S.; Chen, X.; Ding, Y.; Ko, Y.; Shin, Y.J.; Hung, A.H.T.; Chen, B.; Dang, C.; Lakshminarasimhan, D.; Liu, H.; Lin, J.; Lai, K.; Wassermann, L.; Shrivastava, A.; Hsiao, C.; Huang, C.; Chen, J.; Krishnan, L.; Wang, N.; Su, P.; Li, T.; Shih, W.; Yang, Y.; Cangiane, P.; Perlow, R.; Ngai, W.; Huang, H.H.; Chang, J.Y.C.; Jiang, X.; Venes, A.; Gomez, R.R.
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 51(4):845-859 Apr, 2016
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies $1 \text{ mm}^{2}$ area while consuming 300 mW. The LNA consumes 130 mW and occupies $3 \text{ mm}^{2}$ area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum.