학술논문
A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
Document Type
Conference
Author
Natarajan, S.; Agostinelli, M.; Akbar, S.; Bost, M.; Bowonder, A.; Chikarmane, V.; Chouksey, S.; Dasgupta, A.; Fischer, K.; Fu, Q.; Ghani, T.; Giles, M.; Govindaraju, S.; Grover, R.; Han, W.; Hanken, D.; Haralson, E.; Haran, M.; Heckscher, M.; Heussner, R.; Jain, P.; James, R.; Jhaveri, R.; Jin, I.; Kam, H.; Karl, E.; Kenyon, C.; Liu, M.; Luo, Y.; Mehandru, R.; Morarka, S.; Neiberg, L.; Packan, P.; Paliwal, A.; Parker, C.; Patel, P.; Patel, R.; Pelto, C.; Pipes, L.; Plekhanov, P.; Prince, M.; Rajamani, S.; Sandford, J.; Sell, B.; Sivakumar, S.; Smith, P.; Song, B.; Tone, K.; Troeger, T.; Wiedemer, J.; Yang, M.; Zhang, K.
Source
2014 IEEE International Electron Devices Meeting Electron Devices Meeting (IEDM), 2014 IEEE International. :3.7.1-3.7.3 Dec, 2014
Subject
Language
ISSN
0163-1918
2156-017X
2156-017X
Abstract
A 14nm logic technology using 2 nd -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4 th generation high-k metal gate, and 6 th -generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.