학술논문
High Volume Manufacturing Ramp In 90nm Dual Stress Liner Technology
Document Type
Conference
Author
Gehres, R.; Malik, R.; Amos, R.; Brown, J.; Butt, S.; Chan, A.; Collins, C.; Colwill, B.; Davies, B.; Gabor, A.; Le, N.; Lindo, P.; Mello, K.; Meyette, E.; Nastasi, V.; Patrick, J.; Piper, A.; Prakash, D.P.; Rust, T.; Santiago, A.; Su, T.; Van Roijen, R.; Rutten, M.; Slisher, D.; Tessier, B.; Tetzloff, J.; Wehella-Gamage, D.; Wise, R.; Yang, Q.; Yu, C.; Divakaruni, R.; Goth, G.
Source
The 17th Annual SEMI/IEEE ASMC 2006 Conference Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE. :411-416 2006
Subject
Language
ISSN
1078-8743
2376-6697
2376-6697
Abstract
The ability to meet the demand for improved microprocessor performance is made difficult due to the simultaneous need not to increase power consumption. In order to meet these conflicting demands, IBM introduced a 90 nm dual stress liner CMOS technology to improve performance without increasing power consumption (Santiago et al., 2006). In IBM's 300 mm fab, this technology was introduced on multiple microprocessors, designed by different design groups with different architectures. These microprocessors, which were originally designed for a single liner technology, were optimized for systematic yield, power/performance; circuit limited yield (CLY), and random defect limited yield. The benefit of the dual stress liner technology is demonstrated in the power/performance characteristic of a dual core microprocessor and the successful technology ramp is demonstrated by yields of two microprocessors