학술논문

Symmetric BSIM-SOI—Part II: A Compact Model for Partially Depleted SOI MOSFETs
Document Type
Periodical
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 71(4):2293-2300 Apr, 2024
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Silicon-on-insulator
Capacitance
Semiconductor device modeling
Junctions
Integrated circuit modeling
MOSFET
Logic gates
Analog
Berkeley short-channel IGFET model (BSIM)
BSIM-silicon-on-insulator (SOI)
compact model
RF
Language
ISSN
0018-9383
1557-9646
Abstract
In this part, we present a new charge-based symmetric compact model of partially depleted silicon-on-insulator (PDSOI) technology. The model’s core charge calculations are based on the industry-standard Berkeley short-channel IGFET model (BSIM)-BULK platform and fully utilize its speed, robustness, and symmetry properties. Further, the SOI-specific effects (namely, impact ionization, body leakage currents, junction leakage, etc.) are integrated from the industry-standard legacy BSIM-SOI model. The model can accurately capture the floating body effect, which is crucial for PDSOI technology. The linear and nonlinear body contact (BC) models have also been implemented for BC PDSOI devices. The model passes source–drain symmetry tests for both dc and small-signal simulations, resulting in excellent harmonic balance characteristics, critical for RF applications. The model is validated with the state-of-the-art PDSOI device data from the industry.