부산대학교 도서관

A novel compressive cryoreceiver architecture has been proposed combining analog HTS, cryoelectronic, and advanced high-speed GaAs and high-speed/low-power SOI CMOS semiconductor technologies. The proposed receiver will rival the sensitivity of narrowband receivers while providing unprecedented wideband instantaneous frequency coverage with very small size, weight, and power requirements. Future developments will extend the bandwidth capability. HTS tapped-delay-line chirp filters are the enabling technology for instantaneous bandwidths greater than 1 GHz. The filters support dispersive delays as long as 40 ns and time-bandwidth products in excess of 100 using a bonded/thinned-wafer technique to fabricate YBa/sub 2/Cu/sub 3/O/sub 7-/spl part// stripline structures on 125-/spl mu/m-thick, 5-cm-diam LaAlO/sub 3/ substrates. The filters have produced better than -18-dB error sidelobes in a receiver configuration. Preliminary work toward SOI CMOS receiver ASICs is reported. These ASICs will perform pulse data thinning, and binary integration functions. Requirements for A/D converters are discussed.