학술논문

Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on Curve25519
Document Type
Conference
Source
2020 IEEE 27th Symposium on Computer Arithmetic (ARITH) Computer Arithmetic (ARITH), 2020 IEEE 27th Symposium on. :72-79 Jun, 2020
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Engineering Profession
General Topics for Engineers
Computer architecture
NIST
Elliptic curves
Random access memory
Hardware
Field programmable gate arrays
Elliptic curve cryptography
Curve25519
elliptic curve Diffie-Hellman (ECDH)
field-programmable gate array (FPGA)
point multiplication
Language
ISSN
2576-2265
Abstract
This paper demonstrates fast and compact implementations of Elliptic Curve Cryptography (ECC) for efficient key agreement over Curve25519. Curve25519 has been recently adopted as a key exchange method for several applications and included in the National Institute of Standards and Technology (NIST) recommendations for public key cryptography. This paper presents three different performance level designs including lightweight, area-time efficient, and high-performance architectures. Lightweight hardware implementations are used for several Internet of Things (IoT) applications due to their resources being at premium. Our lightweight architecture utilizes 90% less resources compared to the best previous work while it is still more optimized in term of A middot; T (area×time). For efficient implementation from either time or utilized resources, our area-time efficient architecture can establish almost 7,000 key sessions per second which is 64% faster than the previous works. The area-time efficient architecture uses well scheduled interleaved multiplication combined with a reduction algorithm. Additionally, we offer a fast architecture for high performance applications based on the 4-level Karatsuba method and Carry-Compact Addition (CCA). Our high-performance architecture also outperforms previous work in terms of A middot; T. The results show 9% and 29% improvement in A middot; T and A d middot; T (DSP_count×time), respectively. All architectures are variable-base-point implemented on the Xilinx Zynq-7020 FPGA family where performance and implementation metrics are reported and compared. Finally, various side-channel attack countermeasures are embedded in the proposed architectures.