학술논문
An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications
Document Type
Periodical
Author
Brox, M.; Balakrishnan, M.; Broschwitz, M.; Chetreanu, C.; Dietrich, S.; Funfrock, F.; Gonzalez, M.A.; Hein, T.; Huber, E.; Lauber, D.; Ivanov, M.; Kuzmenka, M.; Mohr, C.N.; Garrido, J.O.; Padaraju, S.; Piatkowski, S.; Pottgiesser, J.; Pfefferl, P.; Plan, M.; Polney, J.; Rau, S.; Richter, M.; Schneider, R.; Seitter, R.O.; Spirkl, W.; Walter, M.; Weller, J.; Vitale, F.
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 53(1):134-143 Jan, 2018
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
The graphic DRAM interface standard GDDR5X is developed as an evolutionary extension to the widely available GDDR5. The implementation presented here achieves a data rate of 12 Gb/s/pin on a single-ended signaling interface with 32 IOs for a total memory bandwidth of 48 GB/s. The GDDR5X DRAM relies on the quad data rate operation enabled by a phase-locked loop (PLL), a receiver with a pre-amplifier in a dual-regulation loop and a one-tap digital feedback equalizer (DFE). To support lower performance modes, an additional GDDR5-like operation is provided, which bypasses the PLL. The interface is realized on a conventional high-volume DRAM process to provide a cost-efficient, discrete package 8-Gb DRAM for high-performance graphic cards and compute applications.