학술논문
BEOL Process Effects on ePCM Reliability
Document Type
Periodical
Author
Redaelli, A.; Gandolfo, A.; Samanni, G.; Gomiero, E.; Petroni, E.; Scotti, L.; Lippiello, A.; Mattavelli, P.; Jasse, J.; Codegoni, D.; Serafini, A.; Ranica, R.; Boccaccio, C.; Sandrini, J.; Berthelon, R.; Grenier, J.; Weber, O.; Turgis, D.; Valery, A.; Medico, S.D.; Caubet, V.; Reynard, J.; Dutartre, D.; Favennec, L.; Conte, A.; Disegni, F.; De Tomasi, M.; Ventre, A.; Baldo, M.; Ielmini, D.; Maurelli, A.; Ferreira, P.; Arnaud, F.; Piazza, F.; Cappelletti, P.; Annunziata, R.; Gonella, R.
Source
IEEE Journal of the Electron Devices Society IEEE J. Electron Devices Soc. Electron Devices Society, IEEE Journal of the. 10:563-568 2022
Subject
Language
ISSN
2168-6734
Abstract
The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.