학술논문
Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells
Document Type
Conference
Author
Vega-Gonzalez, V.; Radisic, D.; Choudhury, S.; Tierno, D.; Thiam, A.; Batuk, D.; Martinez, G.T.; Seidel, F.; Decoster, S.; Kundu, S.; Tsvetanova, D.; Peter, A.; De Coster, H.; Sepulveda-Marquez, A.; Altamirano-Sanchez, E.; Chan, Bt; Drissi, Y.; Sherazi, Y.; Uk-Lee, J.; Ciofi, I.; Murdoch, G.; Nagesh, N.; Hellings, G.; Ryckaert, J.; Biesemans, S.; Litta, E. Dentoni; Horiguchi, N.; Park, S.; Tokei, Zs.
Source
2022 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2022 International. :23.2.1-23.2.4 Dec, 2022
Subject
Language
ISSN
2156-017X
Abstract
A new cell routing architecture called vertical-horizontal-vertical (VHV) which requires a two-level (2L) middle-of-line (MOL) scheme has been proposed as a scaling booster to enable 4-track (4T) standard cell (SDC) templates for beyond the 2 nm technology node. In this work, we demonstrate an innovative integration strategy using the semi-damascene technique to implement the 4T VHV, enabling the precise definition of a tight boundary between SDC’s which requires two vias with zero-line extension facing each other and a tip-to-tip (T2T) at the underlaying layer, all at a distance of ’one CD’ of the top layer. As a result, we obtained an average via CD=10.5 nm with a resistance of $24 \Omega$, and a T2T =8.9 nm. Both vias and T2T were self-aligned to the 18 nm pitch layer above.