학술논문

Guest Editors’ Introduction: Hardware Accelerators for Data Centers
Document Type
Periodical
Source
IEEE Design & Test IEEE Des. Test Design & Test, IEEE. 35(1):5-6 Feb, 2018
Subject
Computing and Processing
Components, Circuits, Devices and Systems
Special issues and sections
Hardware
Data centers
Data analysis
Big Data
Neural networks
Language
ISSN
2168-2356
2168-2364
Abstract
It is our pleasure to introduce this special issue on hardware accelerators for data centers. Data centers around the world have been expanding and multiplying rapidly in the last decade with increased internet use, online services, compute consolidation, and data analytics. Hardware accelerators are increasingly important architectural components in the context of data center customization to achieve high performance and lower energy. Prominent companies have introduced FPGA/GPU-based platforms for data centers. For example, IBM’s Coherent Accelerator Processor Interface and Intel’s Quick-Assist Accelerator Abstraction Layer enable the integration of CPUs and FPGAs/GPUs through coherent shared memory. Microsoft built the configurable cloud platform for data centers and demonstrated significant performance improvements for different workloads. In addition to FPGAs and GPUs, application-specific hardware accelerators are being integrated into platforms for widely used workloads such as compression, cryptography, and pattern matching. Google’s tensor processing unit is reported to be used to accelerate machine learning (ML) workloads at Google’s data centers.