부산대학교 도서관

Gordon Moore’s iconic 1965 article unwittingly laid the foundation for a remarkably accurate prediction that has withstood the test of time. His forecast has turned into an industry target, holding immense significance. For decades, downsizing metal and poly pitches effortlessly propelled progress, but now the technical and economical limits of this scaling approach are in sight. Today, the semiconductor industry seeks salvation in the vertical dimension through die stacking, commonly referred to as “chiplet-based design”. However, even these multi-die packages, like all integrated circuits, are susceptible to Murphy’s Law and necessitate rigorous testing for manufacturing defects. Beyond the usual obstacles of test content, accessibility, and cost, chiplet-based ICs present their own unique set of test challenges. This presentation aims to scrutinize these hurdles and explore emerging solutions, if available.