학술논문

A Distributed and Parallel Accelerator Design for 3-D Acoustic Imaging on FPGA-Based Systems
Document Type
Periodical
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 43(5):1401-1414 May, 2024
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Imaging
Sonar
Array signal processing
Ultra wideband technology
Computer architecture
Transducers
Acoustic beams
3-D acoustic imaging
algorithm-hardware co-designed
distributed and parallel architecture
fieldprogrammable gate array (FPGA)-based accelerator
Language
ISSN
0278-0070
1937-4151
Abstract
3-D imaging sonar is crucial in the exploration of marine resources, and the development of portable device with high-imaging quality and high-real-time performance is the general trend. However, traditional framework methods are limited by the huge amount of computation brought by high-quality imaging, making it difficult to implement in engineering. To address this issue, we develop 3-D real-time sonar system in an algorithm-hardware co-designed way. An ultrawideband distributed and parallel subarray beamforming algorithm (UWB-DPS) is proposed for 3-D acoustic imaging. This is a multistage array time-frequency beamforming method under a distributed parallel computing architecture. Based on this, we propose field-programmable gate array (FPGA)-based accelerator. It divides a large sonar receiving planar array into multiple parallel subarrays, and complete the beamforming in two stages, which can reduce the calculation load and speeds up 3-D imaging. For engineering implementation, we optimized the sparseness of the planar transducer array, with a sparse rate as high as 97.7%. The experimental results show that the calculation amount of the proposed UWB-DPS algorithm is reduced to 1/5.7 of the traditional framework algorithm, the imaging performance is effectively improved, and the FPGA-based accelerator outperforms the CPU software implementation by 935 $\times $ .