부산대학교 도서관

This paper reports on a 500 x 500 pixel CMOS image sensor allowing multiple Regions of Interest (RoI) per frame with programmable number and size, aimed at minimizing the amount of data to be delivered off-chip and at reducing its power consumption. The proposed sensor architecture offers large flexibility to face different use case scenarios and it is suitable to any pixel array. The sensor embeds image background subtraction capability and integrates a computing layer which pre-filters the pixels to estimate the Center of Mass (CoM) of the RoIs up to a maximum size of 128 x 128 pixels. The 8 $\mu \mathrm{m}$ pixel sensor is manufactured in a 110 nm 1P4M CMOS technology and occupies 25 $\mathrm{m}\mathrm{m}^{2}$. The chip, operating in standard imaging mode, consumes 4.9 mW at 30 fps.