학술논문
A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS
Document Type
Conference
Author
Damodaran, Raguram; Anderson, Timothy; Agarwala, Sanjive; Venkatasubramanian, Rama; Gill, Michael; Gopalakrishnan, Dhileep; Hill, Anthony; Chachad, Abhijeet; Balasubramanian, Dheera; Bhoria, Naveen; Tran, Jonathan; Bui, Duc; Rahman, Mujibur; Moharil, Shriram; Pierson, Matthew; Mullinnix, Steve; Ong, Hung; Thompson, David; Gurram, Krishna; Olorode, Oluleye; Mahmood, Nuruddin; Flores, Jose; Rajagopal, Arjun; Narnur, Soujanya; Wu, Daniel; Hales, Alan; Peavy, Kyle; Sussman, Robert
Source
2012 25th International Conference on VLSI Design VLSI Design (VLSID), 2012 25th International Conference on. :286-291 Jan, 2012
Subject
Language
ISSN
1063-9667
2380-6923
2380-6923
Abstract
The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.