부산대학교 도서관

Short-gate length epitaxial ${\rm Si}_{1-x}{\rm Ge}_{x}/{\rm Si}$ multi-(core/shell) p-type nanowire (NW) transistors with high-permittivity dielectric and metal gate were fabricated and their electrical properties examined. Silicon NWs were first of all patterned in ultrathin silicon-on-insulator wafers by lithography and etching. Selective epitaxial growth of ${\rm Si}_{0.7}{\rm Ge}_{0.3}/{\rm Si}$ or ${\rm Si}_{0.7}{\rm Ge}_{0.3}/{\rm Si}/{\rm Si}_{0.7}{\rm Ge}_{0.3}/{\rm Si}$ shells was then performed around the Si NW core. Electrical transport measurements showed a hole mobility improvement up to 100% in ${\rm Si}_{0.7}{\rm Ge}_{0.3}/{\rm Si}/{\rm Si}_{0.7}{\rm Ge}_{0.3}/{\rm Si}$ core/shell NWs (70% in wide planar devices) compared with p-type Si reference field effect transistors (FETs). Finally, a drive current enhancement of 60% compared with reference Si-channel devices was evidenced in multi-(core/shell) p-FET NWs scaled down to 15-nm gate length.