학술논문

3D source/drain doping optimization in Multi-Channel MOSFET
Document Type
Conference
Source
2010 Proceedings of the European Solid State Device Research Conference Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European. :368-371 Sep, 2010
Subject
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Signal Processing and Analysis
Logic gates
Degradation
Silicon
Ion implantation
Performance evaluation
Doping
Transistors
Language
ISSN
1930-8876
2378-6558
Abstract
We demonstrate that the integration of in-situ doped Si Source and Drain (S/D) in three-dimensional Multi-Channel Field-Effect Transistors (MCFETs) leads to improved electrical performances. The combination of in-situ doped Selective Epitaxial Growth (SEG) and ion implantation indeed enables to drastically reduce the S/D resistance (down to 72 Ω.µm for nFET and 227 Ω.µm for pFET). Ion implantation induces a small mobility degradation, which becomes negligible in short gate length (L G ) MCFETs. Gate width down-scaling otherwise needed to suppress the overall mobility degradation with L G and obtain the best electrical properties.