학술논문

The effect of first-level cache improvements on the RAMpage memory hierarchy
Document Type
Conference
Source
IEEE AFRICON. 6th Africon Conference in Africa, Africon Africon Conference in Africa, 2002. IEEE AFRICON. 6th. 1:71-76 vol.1 2002
Subject
Aerospace
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Power, Energy and Industry Applications
Robotics and Control Systems
Random access memory
Switches
Context modeling
Delay
Surface-mount technology
Computer science
Traffic control
Interleaved codes
Bridges
Multithreading
Language
Abstract
The RAMpage memory hierarchy is an alternative memory organization which addresses the growing CPU-DRAM speed gap, by replacing the lowest-level cache by an SRAM main memory. This paper presents some modifications to the RAMpage hierarchy. More aggressive first level cache implementations are shown to improve performance of the RAMpage model, when context switches were taken on misses to DRAM.