학술논문
Hardware implementation of an optimized scale-invariant feature detector for robotic applications
Document Type
Conference
Source
2014 IEEE International Conference on Imaging Systems and Techniques (IST) Proceedings Imaging Systems and Techniques (IST), 2014 IEEE International Conference on. :226-231 Oct, 2014
Subject
Language
ISSN
1558-2809
Abstract
A new architecture for the real-time detection of scale-invariant features in image sequences is presented. The system is based on a low-cost smart-camera custom board, developed to target robotic vision applications. Several optimizations of the SIFT detection procedure are proposed in order to achieve robust keypoint detection with high repeatability and recall values. As a result, a high accuracy and resource-efficient implementation of the SIFT detector is presented. The system is pipelined and streams pixel data using a 45 MHz clock, allowing keypoint detection at 150 frames per second, in video sequences with resolution 640×480. Integrating a commodity CMOS sensor, the prototype system displays keypoints at video rate, using only a fraction of the resources of a low-cost FPGA device.